XLS High-Level Synthesis Toolchain for Hardware-Software Co-Design
September 14, 2026
XLS is an Apache 2 licensed High Level Synthesis toolchain that generates synthesizable Verilog and SystemVerilog from high-level functional descriptions. The toolchain allows developers to run hardware designs at native speeds in software before generating functionally identical hardware IP.
HOW THIS AFFECTS YOU
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builderYou can use a software-style methodology to accelerate custom hardware development for AI workloads.