XCENA and Samsung MX1 CXL Device with 3072 RISC-V Cores
August 30, 2026
The MX1 CXL 3.2 device provides up to 2 TB of DDR5 memory expansion via a PCIe 6 x8 interface with 128 GB/s bandwidth. It integrates 3072 RISC-V cores for near-memory compute and supports downstream SSD connectivity using onboard DRAM as a cache.
HOW THIS AFFECTS YOU
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builderYou can offload compute tasks closer to memory to reduce host-side latency and bandwidth bottlenecks.
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founderThis opens new hardware paths for scaling memory-intensive AI workloads without replacing entire server architectures.