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Illinois Team Demonstrates Scalable Sequential 3D Silicon Stacking for Chips
May 30, 2026
Qing Cao's group at Illinois Grainger Engineering has demonstrated a scalable method for directly and sequentially stacking high-performance silicon circuits in 3D, addressing transistor scaling limits imposed by atomic dimensions and quantum effects. The approach adds vertical layers rather than shrinking planar transistors further.
HOW THIS AFFECTS YOU
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researcherSequential 3D silicon stacking at scale is a fabrication milestone relevant to compute density research and future AI hardware architecture.
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investorWorth watching as a potential path to post-planar scaling that could affect long-term compute cost curves for AI infrastructure.